Steeper Subthreshold Swing Attained in Ge-Source Inductive Tunneling FET via Epitaxial Tunnel Layer for Suppressed Point Tunneling

In this paper, we propose an Inductive Line Tunneling FET using Epitaxial Tunnel Layer with Ge-Source and Charge Enhancement Insulation (CEI ETL GS-iTFET). We introduce a P-type region into an N-type substrate by using a Schottky contact to form a PN-iTFET. The CEI ETL GS-iTFET design allows full overlap between the gate and source regions, enhancing line tunneling effects. By incorporating a germanium source and silicon channel, we create a heterojunction that effectively enhances the device conduction current while suppressing ambipolar leakage. In addition, the ETL layer is implemented to eliminate point tunneling path, resulting in a steeper subthreshold swing. Furthermore, a Si
3
N
4
CEI is introduced between the germanium source and the Schottky metal, which reduces carrier losses in the inversion layer and mitigating Fermi Level Pinning (FLP). Simulation results show that the CEI ETL GS-iTFET achieves an average subthreshold swing (SS
avg
) of 30.5 mV/dec, an I
on
of 3.12x10
^-5
A/μm, and an I
on
/I
off
ratio of 1.81x10
¹⁰
at V
D
= 0.2 V.