A 32GS/s 7bit TI-SAR ADC in 28nm for 32Gb/s ADC-Based SerDes Receiver

Wireline receiver front-ends increasingly utilize high-speed time-interleaved ADCs for improved equalization through subsequent digital processing and support for higher-order modulation schemes. A 32GS/s 7bit TI-SAR ADC in 28nm with auto error calibration and trimmed clock is proposed for 32Gb/s ADC-Based SerDes Receiver, achieving stable and high performance with relatively low power consumption. Post-layout simulation results show that the proposed TI-SAR ADC achieves 38.65dB SNDR and 61.41mW power consumption with -1dBFS input signal at Nyquist input frequency.