A 300MS/s 57.6dB SNDR Single-Channel SAR ADC with Accelerated SAR Logic

This paper presents a 10 bit 300MS/s single channel asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 28nm CMOS technology. The improved SAR logic shortens the logic path delay and leads more settling time for the capacitive digital-to-analog converter (CDAC) capacitor rollover. The ADC is designed in TSMC 28nm technology. It achieves SNDR/SFDR of 58.80 dB/81.9dB and 57.6 dB/79.0dB at low and Nyquist input frequency, respectively, resulting in figure of merit (FoM) of 11.3 fJ/conversion-step.