A simulation study about the memory operation of 3D-stacked capacitor-less 1T DRAM cells based on ferroelectric field-effect transistors (FeFETs)

In this paper, a three-dimensionally (3D)-stacked one transistor (1T) dynamic random-access memory (DRAM) based on ferroelectric field-effect transistor (FeFET) has been proposed for an alternative to a conventional 1T-one capacitor (1C) DRAM cell. In addition, its bias scheme has been designed and each cell’s memory operation has been explored by using technology computer-aided design (TCAD) simulation. The results reveal that the unselected cells are perfectly inhibited by applying the inhibition voltage to source/drain, while the selected cell shows program/erase states with a 1.4 V-memory window (MW).