High-Speed FPGA-to-FPGA Interface for a Multi-Chip CNN Accelerator

The size of Convolutional Neural Network (CNN) hardware accelerators is increasing year by year due to the rapidly growing complexity of CNN models. Due to its intensive growth, the prototyping and deployment of CNN accelerators on FPGA devices are becoming challenging. To solve this problem, several researchers have proposed multi-chip CNN accelerator architectures. These architectures utilize a multi-FPGA testing platform that employs high-speed FPGA-to-FPGA communication interfaces. To deal with communication issues in multi-FPGA CNN accelerators, we present an implementation of a high-speed FPGA-to-FPGA interface based on the Aurora protocol. Aurora is a scalable, lightweight, link-layer protocol for high-speed serial communication. To demonstrate the advantages of the FPGA-to-FPGA interface, we designed a multi-chip CNN accelerator using the Aurora interface, which is implemented on Xilinx ZCU102 and Xilinx VU19P FPGAs.