Analysis and Modeling of Non-ideal Effects in SAR ADC

For high resolution SAR ADC, the noise and distortion will significantly degrade the performance, thus should be considered carefully during design. This paper presents a behavioral modeling of SAR ADC in Simulink. The model includes the performance limitations such as clock jitter, capacitor mismatch, sampled KT/C noise for switches, noise and offset of comparator and S/H on-resistance distortion. The simulation results of the proposed model provide guidance in choosing the circuit structure and determine spec breakdown of each block in the SAR ADC, which increases the design efficiency with fast design iterations.