Reconfigurable Cell-Based Systolic Array Architecture for CNN Training Accelerator for Mobile Applications

Systolic array is widely employed in hardware accelerators for Convolutional Neural Networks (CNNs). Since most of previous systolic arrays designed for mobile neural network processors are designed only for inference of CNN models restricting their systolic arrays to support only the forward propagation. Therefore, they cannot process backward propagation which require gradient calculations for weights and feature data. In this paper, we propose a reconfigurable systolic array architecture employing 3x3 cell structures, which can process either forward or backward propagation without requiring additional datapath blocks. It can be configured by on-chip microcode to calculate three convolutional modes: forward convolution, weight gradients, and feature data gradients which are the key components of CNN training process. To evaluate the performance of the proposed architecture, we designed a CNN accelerator consisting of 2304 processing elements (PEs). We implemented it on Xilinx VU19P FPGA and tested it for an object detector CNN, YOLOv2-tiny. We achieved a peak throughput of 921 GFLOPS at a system clock of 150 MHz. Simulation results demonstrated that the utilization of PEs can reach nearly 100% during the convolutional operations.