The Impact of Strain and Layout Dependent Effects on High Frequency Performance and Low Frequency Noise in Nanoscale Devices

SiC strained nMOSFETs with sub-35 nm gate length can realize superior f
T
above 400GHz attributed to more than 20% enhancement of the mobility and transconductance. This super-400 GHz f
T
makes SiC strained nMOS a premium device for mm-wave CMOS circuits design. However, the SiC nMOSFETs reveal a dramatic increase of flicker noise and random telegraph noise (RTN), which may cause worse phase noise and detrimental impact on CMOS oscillator stability. The complex RTN features abnormally long capture and emission time constants (τ
c
and τ
e
) and suggests new mechanism responsible for the anomalously slow trapping and detrapping, due to a significant increase of the relaxation energy from SiC strain. This critical trade-off between high frequency performance and low frequency noise should be considered seriously for an appropriate deployment of high mobility devices and optimization adapted to RF and analog circuits.