Improved BEOL Design Rules With 45-Degree Local Interconnection

In advanced integrated circuit manufacturing technology, continuous scaling down to smaller dimensions rises great challenge in lithography. Leading edge techniques and complexed patterning process have been applied, such as ArF immersion lithography and self-aligned multiple patterning for achieving the 7nm node BEOL metal layer. More flexible 2D layout designs, such as curvilinear or degreed slanted interconnection design, have been considered in advanced technology nodes, in order to continually reduce mask area or mask number. In our previous work, we reported an improved 45-degree interconnection in a Z-like typical pattern for BEOL 193 nm immersion design rules, which showed potentials in mask area reduction and therefore cost-effective advantage in chip manufacturing. In this work, we will study various 2D patterns abstracted from advanced node layouts, with a self-developed aerial image simulator based on the Finite-Difference Time-Domain (FDTD) and the Rigorous Coupled Wave Analysis (RCWA) algorithm. We will firstly discuss the simulated minimum mask area when replacing the orthogonal design to the 45-degree interconnection design. Secondly, we will evaluate this 45-interconnection metal design under EUV lithography process.