1-kS/s 12-bit SAR ADC with Burst Conversion

The proposed 1-kS/s 12-bit SAR ADC performs burst conversion to compensate for the loss of the sampled analog signal due to leakage current in the capacitors of the capacitor-based DAC. The proposed SAR ADC is implemented using a 180 nm 1-poly six-metal CMOS process with a supply of 1.8 V. The proposed burst conversion for low-speed SAR ADCs improves the dynamic performance of ENOB from 10.82 bits to 11.87 bits for an input signal width a frequency of 472.16 Hz at a sampling rate of 1 kS/s. The sleep mode operation between the burst conversions reduces the average power consumption of the SAR ADC from 38.34 uW to 9.70 uW by reducing static power consumption.