Enhancing Performance and Energy Efficiency of Reconfigurable CNN Accelerator

This paper aims to improve the performance, area, speed, and energy efficiency of Convolutional Neural Network(CNN) Accelerator while retaining the accuracy level suggested in [2]. The accelerator is made up of four Diagonal Cyclic Arrays (DCAs), which are a type of systolic array of Processing Elements (PEs). To obtain the enhanced accelerator architecture, we present the following three design optimization methods: decreasing the number of FIFO modules in PEs, minimizing the quantization block size, and modifying the data format for efficient access of DDR DRAM. Compared to the previous CNN Accelerator [2], the proposed architecture based on the three methods has been reduced the FPGA LUT usage by 28.77%, the Flip-Flop count by 6.30%, the Block RAM size by 31.75%, and the DSP usage by 2.41%. In addition, the computation speed has been accelerated by 23% compared to the previous architecture.