Design and Implementation of 32-bit Signed Divider for VLSI Applications

The signed divider is a computational tool that is utilized to conduct the division operation between two signed integers. In the process of division, it is important to note that both the dividend and divisor possess signed values. Typically, the signed divider is employed to execute the division operation between two integers of either 8-bit, 16-bit, or 32-bit size. The present project entails the implementation of a Verilog structural model for a 32-bit signed divider design. The design of the 32-bit divider is simulated using Xilinx Vivado. The design is synthesized, and simulation results are produced in the form of output waveforms using Xilinx Vivado. The physical design results are obtained using the Synopsys tool.