A Framework for Block-Level Physical Design using ICC2 in 14nm Technology

VLSI Technology is all about creating complex chips and SoCs by packing billions of transistors into a single chip. Designing these tiny chips containing very complex circuitry built with billions of transistors is not a simple job, nor a onestep process. Physical Design is a process of converting the RTL netlist into a layout that is manufacture-able (GDS). This process of converting a netlist into a manufacture-able layout involves multiple steps. Physical design helps in physical implementation of circuit and logic cells. Floorplan, Power Planning, Placement, Routing, Static Timing Analysis (STA), and Physical Verification (DRC, LVS) are all included in the backend (Physical Design). Here, the chip is designed in block level design, with the help of IC Compiler II(tool) from Synopsys, with 14nm technology. This is implemented in 14nm technology. Since the project is block level, so 9 metal layers are used for routing. Here, it consists of 65000 standard cells with a maximumfrequency of 650KHz.