Single-Phase Inverter Asymmetrical Quad-Edge Sampling

The delay in the digital control system causes the phase margin and amplitude margin degradation. Conventional asymmetric double-edge sampling reduces the sampling delay by half compared to symmetric double-edge sampling. In the case of a single-phase inverter modulation strategy using unipolar modulation, there are four edges of output voltage in one switching period. This paper proposes an asymmetric quadedge regular sampling PWM pulse generation method to reduce the sampling delay further, improving the phase margin and amplitude margin. Thus, it enhances the system's stability and response speed. The current loop PI control of a single-phase inverter with quad-edge asymmetric regular sampling is implemented on the ZYNQ platform, and experiments verify the correctness of the analysis and the effectiveness of the method.