Design and Demonstration of 3D-Stacked Packaging SiC Power Module with Low Parasitic Inductance and Low Thermal Resistance

Despite the enormous advantages in terms of switching speed, blocking voltage, and thermal conductivity, the silicon carbide (SiC) power device still faces numerous challenges, like unacceptable parasitic inductance and increased thermal resistance, when applied in some emerging applications, such as electric vehicle and renewable energy. Due to the boosted switching speed and higher thermal flux, the power packaging of the SiC power module pursues lower parasitic inductance and thermal resistance. In this paper, the novel 3D packaging configuration for the SiC power modules is proposed and demonstrated. The parasitic inductance is assessed by using the finite element analysis and verified by using the vector network analyzer, while the thermal resistance is confirmed through a multi-physics approach. Additionally, the double-pulse test rig is built to validate the feasibility of the proposed SiC power module with 3D-stacked packaging. The experimental results indicate that the parasitic inductance remains at about 4 nH. It is concluded that the proposed 3D packaging is an effective way for the SiC power module toward low parasitic inductance and thermal resistance.