Verification of Coverage-Driven and Assertion based AXI4 Protocol VIP using UVM

In the present day, the bus protocols which are used for communication between the various IPs on System-on-Chip (SoC) designs have several challenges such as complexity, performance, etc. An Intellectual Property (IP) core is connected to the surrounding interface through SoC buses. This paper aims to verify the features of such bus protocol, the Advanced eXtensible Interface AXI4 Protocol is one among the popular protocols in the Advanced Micro Controller Bus Architecture (AMBA) Family. Using Universal Verification Methodology (UVM) involves creating a comprehensive testbench environment that utilizes the Methodology (UVM) to ensure protocol compliance, Coverage Driven Verification (CDV), and functional correctness of the AXI4 interface. In this paper, we utilize the Verification IP (VIP), with a custom RTL design flow to verify and monitor its behavior. In the VIP design, UVM is used to model the test environment. We mainly focus on verifying the simple AXI4 features using UVM. The test cases for read and write transactions from the same and different address locations, aligned and unaligned transactions, outstanding and out-of-order transactions to validate the working AXI4 Interface with VIP using UVM. Functional coverage is 57.72% for random read and write transaction, it will vary for different testcases and most of the given assertions are passed. We implemented in one of the EDA tools Synopsys VCS 2021.09.