Successive-approximation-register ADC Implementation in 180 nm CMOS Technology for Bio-medical Applications

A microelectronic system designed to handle mixed-signal circuits necessitates the integration of both an analogue-to-digital converter (A/D) and a digital-to-analogue converter (D/A). In this work, our primary focus lies in the realm of wireless biomedical implantable devices. The core objective is to develop a high-performance Analog-to-Digital Converter (ADC) that will effectively interface with various bio-sensors, pacemakers, and other health monitoring devices. This ADC is crucial for establishing seamless communication between the implanted medical devices and the human body, thereby enhancing the overall healthcare system. For biomedical applications high speed is not required but low power is needed. To resolve the power consumption issue in this work A 10-bit Successive Approximation Register (SAR) ADC is implemented in 180 nm CMOS technology with 1 volt supply voltage. Traditional SAR ADC Architecture uses the sample and hold, comparator, SAR logic, and DAC circuit but in this architecture, Sampling is performed through the DAC switches which minimize the overall power consumption of ADC. The simulation results of the circuits show that the ADC archives 8.92-bit ENOB and consumes very low power about 168 nanowatts.