VLSI implementation of ECG feature extraction using Integer Haar Wavelet and EMD Algorithm

The mortality rate due to cardiovascular disease is increasing day by day. Therefore, the need for the development of efficient and reliable healthcare wearable devices is very much essential. In this paper, we present an efficient VLSI implementation for ECG signal denoising and Feature extraction using an integer Haar wavelet Transform and Empirical mode decomposition (EMD) algorithm in terms of area and power. The proposed model is implemented using the Xilinx Artix-7 FPGA family Nexys 4 DDR and realized in very high-speed integrated circuit hardware description language (VHDL). The presented work is validated using the MIT-BIH database from physionet. MATLAB is used to acquire the ECG signal’s data. In Xilinx Vivado, the preprocessing and feature extractions are carried out. Observations found that the proposed method implementation utilizes only 0.398 % of the devices available from Xilinx vivado 2023.1, which is very least, compared to other methods and also with improved PSNR and SSIM values.