Reconfigurable Low Weight Hybrid PUF Design Against Side Channel Attacks

Silicon based PUF uses manufacturing process variations to generate PUF signature to protect from side channel attacks. In this paper a new hybrid PUF design has been implemented on FPGA with programmable delays with Galois RO and glitch architectures. The proposed PUF is immune to existing side channel vulnerabilities such as EM emissions, modelling attacks etc. To generate unit bit response the designed PUF occupies lower area than literature. The novel architecture has improved uniqueness, uniformity, reliability. The randomness is increased by programmable delays, Galois architectures and glitch circuits. The proposed PUF has uniformity of 49.78%, Bit Error Rate (BER) is 0.35%, uniqueness 49.38% and reliability of PUF is around 99.7%.