Comparative Study of Single-Event Effect Tolerance Between Planar and Trench SiC Power MOSFETs

In this paper, the simulation results of heavy-ion induced gate oxide damage and single-event burnout (SEB) in the 1.2-kV rated planar-gate, asymmetrical trench-gate and double trench-gate SiC MOSFETs were presented via Sentaurus TCAD tools. The simulation results show that the planar-gate SiC MOSFET device suffers less gate damage under heavy-ion irradiation and the trench-gate SiC MOSFETs have a relatively higher SEB threshold. All architectures were proven to have similar performance and failure mechanism in single event effect (SEE).