FPGA Architecture of Bilateral Filter for Image-Denoising

Denoising a picture is an essential activity in the area of image processing and has a wide variety of applications, spanning from computer vision to medical imaging. In this scenario, the Bilateral Filter has emerged as a potent tool that successfully reduces noise while still keeping information about the edges of the image. In this article, an FPGA architecture for a wavelet-based Bilateral Filter that is intended to speed up picture denoising operations is presented. Real-time denoising of high-resolution photographs may be accomplished with the help of the suggested FPGA design, which makes use of the parallel processing capabilities of FPGAs. Because it uses a method that is based on wavelets, the filter not only maintains the picture features but also adjusts to the local characteristics of the image, which enables it to function reliably in a wide variety of contexts. The experimental findings show that the FPGA-based Bilateral Filter is successful in denoising pictures while yet maintaining a low latency. When compared to software-based solutions, the performance of the suggested architecture is much higher, which makes it an extremely useful tool for picture denoising in settings where resources are limited.