Design and Performance Analysis of 3-Fin 08 nm Physical Gate Length SOI FinFETs Employing Gate Stacked High-K Dielectrics

The continuation of the scaling of FinFETs in the nano regime guaranteed the continuance of semiconductor industry with the fabrication of reliable, high performance and low power devices. The Short Channel Effects (SCEs) were effectively suppressed by these Trigate FinFETs while lowering the leakage currents further. However, as the FinFETs were scaled below 22 nm gate lengths, the SCEs amplified. The gate oxide thickness was reduced to suppress the SCEs but the leakage currents deteriorated. Therefore, to reduce the leakage currents along with improved SCEs, the replacement of the gate oxide with high permittivity dielectrics like Zirconium Dioxide, Hafnium Oxide, Aluminum Oxide and Silicon Nitrate were needed. The motivation of this paper is the development a 3 Fin SOI FinFET at a physical gate length of 08 nm where the gate oxide of each fin consists of a stacked combination of 0.5 nm of high-k dielectrics atop a 0.5 nm layer of SiO
2
to control the leakage currents and other SCEs. The use of 3-Fin structures significantly enhances the drain current while the gate stack high-k materials reduce leakage currents leading to higher switching speeds for faster CMOS fabrication and optimized device performance.