A Simplified Design of Fast Error Correction Module Using Reed-Solomon Code

A Forward Error Correction (FEC) module realized in hardware on Field Programmable Gate Array (FPGA) is having more significance in the practical control applications. This is due to its ability to process the data (encoding and decoding) much faster through FPGA and able to overcome the limitations of data transfer. But the real challenge in such a design is the run time reconfiguration. Lot of researches happening on this issue and there is no standard reference available. Also, there is no flexibility in the existing software solutions. Considering this, in this work, the authors were tried to perform a basic software implementation of FEC module using Reed Solomon (RS) code on a custom made system-on-chip with a soft core processor followed by the RTL level implementation of RS code which can be dynamically controlled. To achieve faithful data transfer between two terminals, two NIOS II SOCs (System on Chip) were built on FPGAs. For the implementation, Altera Cyclone III FPGA starter board was used. Quartus II 10.1 Design Software with NIOS II Embedded Design Suite adopted for configuring the FPGA. The performance of the developed model is verified by monitoring the content message bits before and after corruption of data at the receiver terminal. A comparative study was carried out between hardware and software implementations.