Sense Amplifier Offset Error Correction Method for High Speed Systems

The offset error correction method for high-speed systems is presented. In high-speed systems comparator offset variation becomes more important. This variation has an impact on the proper work of the calibration blocks. The proposed method corrects offset error of sense amplifier through hysteresis to provide precious value of output stage and avoid functional fails. The offset of comparator is critical in many systems such as Double Data Rate (DDR) and can cause slew rate mismatch by generating incorrect slew rate code through finite state machine (FSM). The proposed architecture can be used in high-speed systems where data rates are 10Gbps or higher. Modern high-speed systems require less than 2mV offset and proposed method can be used in special input/output circuits of several standards such as Double Data Rate (DDR), Universal Serial Bus (USB) and Peripheral Component Interconnect (PCI).