An Area-Efficient Coarse-Grained Reconfigurable Array Design for Approximate Computing

There has recently been significant attention towards CGRAs (Coarse-Grained Reconfigurable Arrays) due to their high processing performance, power savings, and programming flexibility. Streaming applications, such as signal processing and image processing, are key target domains of CGRAs. These applications often allow processors to calculate computation results with tolerable errors, leveraging the limitations of human perception. Approximate computing is a promising technique which exploits the acceptable error to reduce the complexity of circuits. This paper explores the use of approximate computing techniques to reduce circuit complexity and improve the efficiency of CGRAs. We analyze the hardware overhead associated with traditional redundant CGRA designs and propose an area-efficient design strategy. Our evaluation results demonstrate a potential 35% reduction in area. Furthermore, considering several benchmark application mappings onto our proposed CGRA design, the proposed design maintains area efficiency and achieves around 20% of power reduction.