A Low-Stall Methodology for an Interleaved Processor State Replication

In this paper, we present a novel hardware approach, which allows a simultaneous program execution in parallel to a state transfer. We introduce an interleaved state replication methodology and a corresponding processor architecture. Our interleaved state replication methodology is applicable for fast context switches which are of crucial importance in mixed criticality systems. To enable our novel methodology for interleaved state replication directly on the hardware level we propose an appropriate processor architecture. On this architecture we implement various transfer strategies and investigate them on representative workloads. Our experiments demonstrate a program execution without stalls in the best case, while the complete state is replicated in parallel. The interleaved state transfer achieves an average 84% reduction in stall cycles compared to state of the art.