Experimental Evaluation of Josephson Balanced Comparators Toward 100 GHz RSFQ Circuits

The Josephson balanced comparator (BC) is a decision-making element and a key building block for all RSFQ logic cells. The comparator is usually characterized by two parameters: gray zone and threshold value. Both parameters depend on the comparator's design, the design of a BC's driver, as well as temperature and frequency of operation. In this article, we focus on the high-frequency properties of the balanced comparators designed for the Nb SFQ5ee fabrication node at MIT-LL. RSFQ circuits, fabricated at this node, operate nowadays routinely at about 50 GHz. We demonstrate that a further increase of the operational frequency up to 75 GHz with a bit-error rate (BER) of 10
⁻¹⁴
can be achieved by optimizing the comparator's driver design. We estimate BER of 10
⁻³
at 100 GHz, which is not enough for complex circuits. An acceptable BER at 100 GHz requires additional optimization of design and fab.