A Mixer-First Receiver With On-Demand Passive Harmonic Rejection

This letter presents a mixer-first RF receiver that: 1) nominally operates in a low-NF
$N$
-path filter mode; 2) features an on-chip harmonic blocker detection circuit running in the background; 3) switches to a harmonic rejection mode upon detection of harmonic content; and 4) passively rejects harmonic blockers through a current-mode circuit that uses resistor sizing to set the amplitude of each path, but with capacitive termination to minimize conversion loss to 1.9 dB while providing a sharp, down-converted filter response. Implemented in 65nm CMOS, the receiver achieves 36/40-dB HR3/5,+21 dBm IIP3, +1 dBm blocker 1-dB compression point (B1dB) and 4/8-dB NF while consuming 10–23 mW.