A Highly Digital 143.2-dB DR Sub-1° Phase Error Impedance Monitoring IC With Pulsewidth Modulation Frontend

This article presents a highly digital impedance monitoring IC that achieves a wide dynamic range (DR) (>140 dB), small area (~0.2
$\text {mm}^{{2}}$
), and small phase error (< 1°). It consists of a square-wave current stimulator, a pulsewidth modulation (PWM) frontend, and two continuous-time (CT) delta-sigma (
$\Delta \Sigma $
) modulators. The stimulated signal is encoded using the PWM frontend and the complex impedance information can be extracted by in (I) and quadrature (Q) demodulation. Each output can then be digitized using a second-order digitally controlled oscillator (DCO)-based CT
$\Delta \Sigma $
modulator. This highly digital architecture enhances energy and area efficiencies. The prototype IC occupies only 0.21
$\text {mm}^{{2}}$
in a 65-nm CMOS process. It achieves a DR of 143.2 dB and a resolution of 17.7
${\text {fF}}_{\text {rms}}$
for capacitance detection within a conversion time of 16 ms. Despite the use of a square-wave stimulator, the PWM frontend allows achieving a small phase error of 0.675°, while consuming only 310.9
$\mu \text{W}$
from a 1.2-V supply.