A 85-Gb/s PAM-4 TIA With 2.2-mApp Maximum Linear Input Current in 28-nm CMOS

This letter presents a 100-Gb/s CMOS PAM-4 transimpedance amplifier (TIA) with multimilliampere maximum linear input current. A low-noise high-linearity TIA architecture is proposed, leveraging the reconfigurable front-end (FE) TIA and the continuous time linear equalizer (CTLE) synced at multiple gain modes. Implemented in a 28-nm CMOS technology, the TIA achieves bandwidth of more than 24 GHz with transimpedance gain of 65 dB
$\Omega $
, while showing an acrlong IRN current density of 10.4 pA/
$\surd $
Hz. The maximum linear input current reaches 2.2 mApp and the total harmonic distortion (THD) is less than 3% for an output swing of 600 mV
$_{\rm pp, {\mathrm{ diff}}}$
. The chip consumes power of 56 mW from 1.4 and 1.1-V supply.