A 0.4–6-GHz Blocker-Tolerant Receiver in 65-nm CMOS With Bandwidth-Extended Technologies for Future V2X Applications

A 0.4-6 GHz multi-mode blocker-tolerant receiver implemented in 65 nm CMOS process is presented. A
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-type Capacitor-Inductor-Capacitor (CLC) current matching network is proposed for N-path-based bandpass low noise transconductance amplifier (BLNTA) to extend bandwidth. Moreover, an improved NAND-based windmill divider is proposed to expand the upper frequency of clocks to at least 8 GHz in all corners. Adaptive bias circuits are introduced to stabilize performance. Measurement results show that the receiver can achieve frequency selectivity in all 0.4-6 GHz bands. The receiver’s maximum gain is 37 dB, with the minimum double sideband (DSB) noise figure (NF) of 3.4 dB. The in-band (IB) input third-order intercept point (IIP3) is −1.2 dBm, and the out-of-band (OoB) IIP3 is 13.9 dBm. The overall power consumption is 46.5 mW+2.5 mW/GHz. The receiver aims to support cellular protocols for vehicle-to-everything (V2X) applications.