A Low-Power Hierarchical CNN Hardware Accelerator for Bearing Fault Diagnosis

This article presents a 2-D hierarchical convolutional neural network (HCNN) hardware accelerator that is implemented in a 40-nm CMOS technology for Case Western Reserve University (CWRU) bearing fault diagnosis. The hierarchical structure of the convolutional neural network (CNN) contributes to a reduction in both power consumption and computation time. The entire neural network parameters are 29k, and the total CNN computation is completed within 330 000 cycles, showcasing its real-time capability. The proposed design substantially diminishes the number of cycles necessitated for hardware calculations. Furthermore, this work incorporates Gaussian white noise into the vibration signal dataset for signal-to-noise ratio (SNR) analysis. A noisy training dataset is added to the original dataset for neural network training to improve the accuracy. In summary, the postlayout simulation of the proposed design facilitates real-time fault diagnosis at a clock frequency of 100 MHz, achieving an accuracy of 95.31%, and a power consumption of 65.608 mW. Also, when the proposed HCNN circuit was implemented on a field-programmable gate array (FPGA) evaluation board, it consumed 0.533 W at 55 MHz.