An FPGA-Based Hardware Architecture for P + M Class PMU Using Accuracy-Aware O-Spline Filter Selection and Modulation Detection

Phasor measurement unit (PMU) is an innovative breed of electronic equipment in the power industry. Improving the accuracy and performance of PMUs in steady-state and dynamic signal conditions is still a challenge. In this work, we propose a phasor estimation method based on O-spline filters. These filters have already been presented in the form of nonic O-splines (NOs) for phasor estimation. We show that their accuracy can be enhanced for different PMU classes and reporting rates. To this end, we find optimized design parameters for these filters, which result in the lowest sum of scaled errors for different signal models. Then, we employ a new real-time modulation detection method to select the proper filters according to the signal’s spectral contents. The study is carried out for both P and M class PMU for three standard reporting rates. The proposed method shows better accuracy in several steady-state and dynamic tests compared to the i-IpDFT method. Because of the massive computational complexity of the designed filters, a field-programmable-gate-array (FPGA) based hardware architecture is proposed to implement the phasor estimation method.