A Physics-Informed Scaling Method for Power Electronic Converters in Power Hardware-in-the-Loop Test Beds

Power hardware in the loop (PHIL) is a modern experimental technique that allows the emulation of a full-scale converter (FSC) with the combination of a scaled-down converter (SDC), a power amplifier, and a real-time simulator, thus enabling the study of real-time interactions of power electronics with large power systems. However, assembling an accurate scaled-down replica of an FSC with off-the-shelf laboratory SDCs is practically impossible due to a mismatch in per unit losses, as well as in the impedance of the
$L/LC/LCL$
filter. Consequently, the scaled-up power flow capability of SDCs differs from that of FSCs, restricting emulation to smaller regions of the four quadrants than those corresponding to the FSCs' nominal active and reactive capacity. These PHIL test beds cannot be used to emulate FSCs demanding bidirectional active and reactive power flow. Any scaling method on SDCs, emulating the entire operation of FSCs, demands underutilization of SDCs, reducing the advantages of PHIL tests. This article, therefore, proposes a physics-informed scaling method that exploits power capability curves to emulate FSCs in all four quadrants of operation. This method is independent of SDC topology, filter type, and interfacing methods. A visual identification of semiconductor device constraints bounding the emulation is also presented, utilizing the physics of converter control. A theoretical analysis of the proposed method is presented, followed by validation with MATLAB simulations and experimental tests using a 50-kVA SDC.