Clock Frequency Optimization of a Compensated Spread-Spectrum Controller in Buck Converters

This research investigates the spread-spectrum technique’s impact on buck converters, with a focus on electromagnetic emissions and output voltage ripple. The ripple, attributed to constant delay time in the PWM generator, induces changes in the duty cycle as the switching frequency varies due to the spread-spectrum technique. To alleviate this, a time delay compensation mechanism recalculated at each switching frequency change is proposed. To address duty cycle inaccuracies from integer calculations in a digital core, a remainder accumulator in time delay calculation is introduced. A numerical model parametrized by the controller’s clock frequency and spread-spectrum resolution examines duty cycle error, ripple, and EMI peak reduction. Findings indicate that the proposed compensator and accumulator reduce duty cycle error while maintaining comparable ripple and achieving similar EMI peak reduction. EMI peak reduction plateaus at higher clock frequencies, suggesting an optimal clock frequency. Experimental results from an FPGA prototype corroborate the model and simulations, showing substantial duty cycle error reduction, comparable ripple, and maximized EMI peak reduction. The study thus illustrates the spread-spectrum technique’s potential in buck converters, providing an optimal configuration for EMI reduction and minimizing duty cycle error and ripple.