Heterogeneous Monolithic 3-D IC Designs: Challenges, EDA Solutions, and Power, Performance, Cost Tradeoffs

Monolithic 3-D (M3D) integrated circuits (ICs) introduce a new aspect to the physical design problem by stacking dies vertically. We introduce a novel heterogeneous design for M3D ICs, which utilizes different technology processes for each die. We also propose enhancements to the design flow and improved partitioning methods to support our suggested heterogeneous 3-D IC design. We perform 3-D partitioning with low-cost, low-power, and low-performance cells on the bottom die, and vice versa on the top die. This arrangement allows us to create a high-performance 3-D IC that is more cost-effective and power-efficient than both the 3-D and 2-D homogeneous implementations. We demonstrate these advantages using four different netlists, showing up to a 23% improvement in performance per cost (PPC), and a 16% improvement in power delay product (PDP) when comparing our heterogeneous M3D design to the best 2-D designs.