A 6h ± 1 Repetitive Scheme for the Three-Phase CHB Seven-Level Converter Used in an APF Application

This work proposes a controller for a three-phase cascade H-bridge seven-level converter used in a shunt active power filter (SAPF) application which includes a repetitive scheme for the compensation of harmonics 6h ± 1. A model description in terms of more appropriate variables facilitates the control design process as it can be split into three independent loops, namely an inner current tracking loop, and outer voltage regulation and balance loops. As a first approach, the inner current loop includes a bank of resonator scheme as the harmonic distortion compensator (HDC), which is later replaced by a repetitive scheme with the aim to reduce the computational effort. However, the required delay to implement the delay lines in the repetitive scheme turns out to be a function of the fundamental frequency, which in real applications may exhibit gradual variations. This entails an implementation issue referred to as the variable fractional delay (VFD), which is compensated by incorporating a Farrow structure. The performance of the proposed controller has been tested in an SAPF based on a cascade H-bridge seven-level converter prototype.