A New Hardware Architecture for SVPWM Technique Based on the Taylor Decomposition

A novel hardware digital architecture for the space vector pulsewidth modulation (SVPWM) technique is proposed and based on a novel algorithm for the evaluation of the dwell times. Indeed, the complexity of the calculation of trigonometric functions is solved by introducing a Taylor series decomposition and using a convenient definition of the space vector
$\alpha -\beta $
plane. Our architecture can modify the dwell times as a function of the fundamental and switching frequencies, of the phase and of the modulation index. Compared to other techniques, it avoids the use of external reference voltages as well as of the precalculated dwell times, like for the LUT-based architectures. Although it can be implemented in several logic devices, an Altera Cyclone V field programmable gate array (FPGA) is used as a digital controller of a three-phase power inverters and its resources are 16% and 2%, respectively, of the look-up tables and of the flip flops. Several cases are studied in order to show the goodness of the output waveforms during the real-time variations of the inputs.