Fault simulation Framework using PyUVM

This paper presents a fault simulation environment developed using PyUVM to address challenges in simulating faults during the manufacturing process of integrated circuits (ICs). The two main challenges tackled are simulating pre-manufacturing fault behavior and overcoming performance issues. The contributions of this work include expanding the fault simulation capacity beyond existing fault simulation methodologies, improving simulation time through efficient algorithms, and enabling compatibility with Universal Verification Methodology (UVM) and SystemVerilog testbenches. The environment allows for injecting various types of faults into a design, reporting the resulting behavior, and facilitating comprehensive analysis under different fault scenarios. The proposed solution enhances fault simulation capabilities, reduces simulation time, and provides compatibility for seamless integration with existing designs and verification methodologies.