Computational-Based Advanced Encryption Standard (AES) Accelerator

The demands of high-level security and performance for resource-constrained SoC represent real challenges. Consequently, the dedicated accelerators are designed to deliver a high-quality function with minimal costs. This paper introduces a high-performance Advanced Encryption Standard (AES) accelerator that minimizes the area and power overhead. The suggested design replaces the LUT-based implementation of the substitution block (SBox) with a combinational circuit to break the fixed memory accesses and reduce power consumption. The proposed architecture reduces the hardware complexity by integrating the transformation and its inverse in one block and utilizes one key expansion block. The suggested accelerator outperforms the standard implementation of encryption by 25% and takes the benefits of the design aspects that are utilized in it.