A Novel Architecture of CXL Protocol Data Link Layer for Low Latency Memory Access

With the increase in memory-intensive applications, there is a need to provide low latency paths for memory access and coherent caching between host processors and storage devices. This paper proposes a novel architecture for the Data Link Layer of Compute Express Link (CXL) protocol, as defined in CXL Specification Revision 2.0. The architecture presented here contains the transmission and reception chains, which ensures the reliable conveyance of the packets between two CXL components using the CXL protocol. This paper explains how the proposed architecture ensures reliable data conveyance, responses and requests, through the addition of a 16-bit Cyclic Redundancy Check (CRC) to each 512-bit FLow control unIT (FLIT) in the transmitter side, and how the packets are processed in receiver side. The architecture is intended to have simple implementation in addition to having minimum datapath delays. The whole architecture is designed using HDL then verified using test-benches for different protocol scenarios to make sure that the functionality of the system is achieved. In addition, the whole design is synthesized using United Microelectronics Corporation (UMC) 130 nm [1] and Taiwan Semicomductors Manufactor Company (TSMC) 28 nm [2] technologies to get the maximum achieved frequency and calculate the corresponding power and area. The proposed hardware implementation manages to work up to 1 GHz using TSMC 28 nm technology and 438.59 MHz using UMC 130 nm technology. Its estimated dynamic and leakage power consumption by UMC 130 nm technology at 1 GHz are 95.3698 mW and 171.17 mW, respectively. In addition, its area cost extracted after synthesis is 242124.8 $\mu \mathrm{m}^{2}$.