AUTG: An Automatic UVM-based TestBench Generator for VLSI Chip Design Verification

VLSI (Very-Large-Scale Integration) chip design is a complex process, especially with the increasing systems complexity. This process comprises many steps. Each design step has a corresponding verification step. Chip design verification is the process of ensuring that the RTL (Register Transfer Level) design of a chip captures exactly the chip specifications. This process is time and resource-consuming. Almost 70% of the chip design effort is spent on verification. Thus, improving the verification productivity will accelerate the overall chip design process, and make it more efficient. Automation is an efficient technique for accelerating the verification process. There are many attempts in the literature for TestBench auto-generation. Although these techniques contributed to design verification productivity improvement, these tools are not easy to use, too expensive, and have limited features. UVM (Universal Verification Methodology) is a standardized and popular methodology for VLSI chip design verification. In this paper, we propose AUTG (Automatic UVM TestBench Generator). AUTG receives the GRef (Golden Reference) and the port list of the DUT (Design under Test). Then, it transforms the GRef into a complete reference model with checkers. Moreover, it generates the components of the UVM-based TestBench of the DUT. AUTG has been implemented and tested with multiple benchmarks. The experimental results showed that AUTG can successfully generate functional verification code. The auto-generated code was tested, and it successfully hunted all the planted bugs in the benchmarks’ RTL designs.