Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration

In this article, we present a new analytical 3-D placement framework with a bistratal wirelength model for faceto-face-bonded 3-D ICs with heterogeneous technology nodes based on the electrostatic-based density model. The proposed framework, enabling GPU acceleration, is capable of efficiently determining node partitioning and locations simultaneously, leveraging the dedicated 3-D wirelength model and density model. The experimental results on ICCAD 2022 contest benchmarks demonstrate that our proposed 3-D placement framework can achieve up to 6.1% wirelength improvement and 4.1% on average compared to the first-place winner with much fewer vertical interconnections and up to
$9.8\times $
runtime speedup. Notably, the proposed framework also outperforms the state-of-the-art 3-D analytical placer by up to 3.3% wirelength improvement and 2.1% on average with up to
$8.8\times $
acceleration on large cases using GPUs.