VLSI implementation of the variable length pipeline scheme for data-driven processors

In this paper, the implementation of the VLP scheme on a VLSI chip is described. The implemented circuit is an improved from of the EDTL and operates as a FIFO(First0In First-Out memory). The advantage of data-driven processors can be maximized with this high-speed FIFO, namely with the VLP scheme, which assures a high performance in parallel processing.