Microcontroller design for the Montana EaRth Orbiting Pico-Explorer (MEROPE) Cubesat-class satellite

Montana State University's Space Science and Engineering Laboratory (SSEL) under support from the Montana NASA Space Grant Consortium is engaged in an Earth orbiting satellite student project that will carry a reproduction, using current-day technology, of the scientific payload flown on Explorer-1 in 1958 into a 650 km sun-synchronous polar orbit. On-board operations will be commanded by a Motorola MC68HC812A4 (HC12) microcontroller, chosen for its ease of use, processing power, and intrinsic features. Accompanying this will be an Integrated Device Technology CMOS Supersync First-in, First-Out (FIFO) IDT72291 150 Kbyte RAM chip, used for storing scientific data and system telemetry before downlink to ground station. The RAM was selected for the simplicity of the FIFO data flow. The HC12 is responsible for controlling antenna deployment, communication handling, and other system parameters. System interrupts allow the HC12 to seamlessly collect payload data, attitude data, battery conditions (voltage, current, charge state, and temperature), bus voltage, bus current, processor temperature, and stability of the payload high voltage power supply. This paper describes MEROPE's computer subsystems in detail.