Experimental Investigation and Hardening of Single-Event Gate Rupture in 100-V Spl-Gate Trench VDMOS

This article presents the results of heavy-ion experiments conducted on a 100-V split-gate trench VDMOS (SGT VDMOS) at various bias voltages. The experimental findings reveal that when an incident heavy-ion strike is perpendicular to the device, no failures were attributed to Single Event Burnout (SEB), whereas all failures were attributed to single event gate rupture (SEGR). Subsequent fault analysis indicates the gate oxide on the upper side wall in the termination has suffered damage. To mitigate this issue, a SEGR hardened termination structure with double
${p}$
-columns is proposed and analyzed using Sentaurus TCAD. The introduction of double
${p}$
-columns creates a depletion region near the gate oxide, effectively reducing the oxide field below the critical breakdown field. The effectiveness of the proposed radiation-hardened structure in improving SEGR tolerance has been analyzed.