A 2.1pJ/bit 56-Gb/s PAM-4 CDR with Integrated AFE in 28nm CMOS for Direct-Modulated Laser Drivers

This paper presents a 56-Gb/s PAM-4 reference-less bang-bang clock and data recovery circuit (CDR) with an analog front-end (AFE) for direct-modulate laser drivers applications. A quarter-rate structured CDR has been implemented, along with the integration of transition selection functionality to handle the locking of CDR for PAM-4 signals. Furthermore, a dynamic comparator has been introduced, capable of comparing, demultiplexing, and thermometer encoding PAM-4 signal levels. The proposed CDR has been implemented in a 28-nm CMOS process, achieving an energy efficiency of 2.1 pJ/bit. The recovered 7 GHz clock displays an integrated jitter of 1.43 ps across a 1 GHz bandwidth.