Contents I. Introduction
With the rapid development of electronic medical devices, aerospace, automotive, and radar fields, the demand for high-precision DACs is also rising. For example, in control fields such as radar systems, the accuracy and linearity of DACs directly affect the performance indicators of the system [1], requiring the design of high-precision and high-linearity DACs. There are mainly charge-redistribution type, current steering type, and resistor divide type structures for DACs. Charge-redistribution DACs have higher resolution but poor monotonicity. They require high matching accuracy of capacitors in the circuit and often occupy a large chip area [2]. Therefore, it is rarely considered to achieve a resolution above 12 bits using charge-redistribution DACs. The structures suitable for high-precision and high-linearity DACs are mainly resistive divider type and current steering type. When the accuracy of the current steering DAC exceeds 10 bits, the units current source control switch regularly adopts a segmented decoding structure. Usually, the Most Significant Bits (MSB) use thermometer decoding, and the Least Significant Bits (LSB) use binary-weighted decoding. However, in this way, the current steering type DACs may produce large glitches in certain specific input codes, such as transitioning from all 1 to all 0 for low bits and carrying over to the high-order bits, which introduces the risk of code error [3]. Resistive divider DACs have the advantages of a simple structure and good linearity. However, in standard CMOS processes, most resistive divider DACs can only achieve an accuracy of 8–9 bits [4]. This is mainly because the accuracy is primarily limited by the matching of the resistors. As the resolution of the DAC increases, the number of resistors needs to increase exponentially, and the impact of mismatch in the resistor string will be greater.
