Metrology Evaluation Indicators of Gate Line End Patterning of SRAM by Using SEM Contour Extraction

Critical dimension scanning electron microscope (CDSEM) is a crucial tool for measuring the dimensions of patterns, enabling sub-nanometer precision measurements after lithography and etching processes on wafers. However, the measurements performed by CDSEM are focused on a single process layer, and the measurement types are limited. Which makes it difficult to comprehensively evaluate the overall pattern process by considering adjacent layers. In this study, several evaluation indicators are proposed for the gate and active area (AA) stack layer structure of static random-access memory (SRAM) by using CDSEM contour extraction and graphical calculations. This research realizes more sensitive evaluation standards, which can be utilized in the Statistical Process Control system (SPC) of semiconductor fabrication to enhance pattern process control.