Design of 40Gb/s PAM4 Signal SerDes Low Power CMOS 64:4 MUX

This paper designs a low-power CMOS 64:4 MUX circuit for 40Gb/s PAM4 signal SerDes system. The circuit uses UMC28nm process with a 1.05V voltage. The circuit structure is composed of 4-stage cascaded 2:1 MUX and configurable clock module. Clock control sampling of 2:1 MUX per stage is used in a configurable clock scheme to guarantee maximum and provide clock drive. To reduce power consumption, 5Latch and 3Latch 2:1 MUX schemes are used. For different transmission rates, each stage 2:1 MUX using different structures to implement. Improving the robustness of the circuit, CMOS 64:4 MUX enables the conversion of 64-bit 625Mb/s parallel data into 4-bit 10Gb/s serial data under various PVT conditions. Abstract: This article designs a low-power CMOS 64:4 MUX circuit for the 40Gb/s PAM4 Signal SerDes system. The circuit adopts UMC28nm technology and a 1.05V power supply voltage. The circuit structure is composed of a 4-stage cascaded 2:1 MUX circuit and a configurable clock module. Using a configurable clock scheme, clock control sampling is performed on each stage of 2:1 MUX to ensure maximum timing margin and provide clock drive. In order to reduce power consumption, the 5Latch and 3Latch 2:1MUX scheme is adopted. For different transmission rates, 2:1MUX at each stage is implemented with different structures, which improves the robustness of the circuit. Under various PVT conditions, CMOS 64:4 MUX achieves the conversion of 64 bit 625Mb/s parallel data into 4 bit 10Gb/s serial data.